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Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter

Analog Devices

Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter RSS Sample
  • Darmowa próbka
MPN:
AD9152
Producent:
ANALOG DEVICES
Dodany do bazy:
Ostatnio widziany:
Zmiana ceny:
-100% (19.01.2025)
Poprzednia cena:
57.78

The AD9152 is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a maximum sample rate of 2.25 GSPS, permitting a multicarrier generation up to the Nyquist frequency. The DAC outputs are optimized to interface seamlessly with the ADRF6720 analog quadrature modulator (AQM) from Analog Devices, Inc. An optional 3-wire or 4-wire serial port interface (SPI) provides for programming/readback of many internal parameters. The full-scale output current can be programmed over a range of 4 mA to 20 mA. The AD9152 is available in a 56-lead LFCSP. The AD9152 is a member of the TxDAC+® family.

PRODUCT HIGHLIGHTS

*

Ultrawide signal bandwidth enables emerging wideband and multiband wireless applications.

* Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.

* JESD204B Subclass 1 support simplifies multichip synchronization in software and hardware design.

* Fewer pins for data interface width with the serializer/deserializer (SERDES) JESD204B four-lane interface.

* Programmable transmit enable function allows easy design balance between power consumption and wake-up time.

* Small package size with an 8 mm × 8 mm footprint.

APPLICATIONS

*

Wireless communications

* Multicarrier LTE and GSM base stations

* Wideband repeaters

* Software defined radios

* Wideband communications

* Point to point microwave radios

* LMDS/MMDS

* Transmit diversity, multiple input/multiple output (MIMO)

* Instrumentation

* Automated test equipment

* Supports input data rates up to 1.125 GSPS

* Proprietary low spurious and distortion design

* Single carrier LTE 20 MHz bandwidth (BW), ACLR = 77 dBc

at 180 MHz IF

* SFDR = 72 dBc at 150 MHz IF, −6 dBFS

* Flexible 4-lane JESD204B interface

* Multiple chip synchronization

* Fixed latency

* Data generator latency compensation

* Selectable 1×, 2×, 4×, and 8× interpolation filter

* Low power architecture

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