14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The AD9641 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.

The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.

The flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

APPLICATIONS

* Communications

* Diversity radio systems

* Multimode digital receivers (3G and 4G)

GSM, EDGE, W-CDMA, LTE,

CDMA2000, WiMAX, TD-SCDMA

* Smart antenna systems

* General-purpose software radios

* Broadband data applications

* Ultrasound equipment

PRODUCT HIGHLIGHTS

* An on-chip PLL allows users to provide a single ADC

sampling clock. The PLL multiplies the ADC sampling clock

to produce the corresponding JESD204A data rate clock.

* The configurable JESD204A output block coded data rate

supports up to 1.6 Gbps.

* A proprietary differential input maintains excellent SNR

performance for input frequencies up to 250 MHz.

* Operation is from a single 1.8 V power supply.

* The standard serial port interface (SPI) supports various

product features and functions, such as data formatting

(offset binary, twos complement, or gray coding), controlling

the clock DCS, power-down, test modes, voltage

reference mode, and serial output configuration.

* JESD204A coded serial digital outputs

* SNR = 73.7 dBFS @70 MHz and 80MSPS

* SNR = 72.8 dBFS @70 MHz and 155MSPS

* SFDR = 94 dBc @ 70 MHz and 80 MSPS

* SFDR = 90 dBc @ 70 MHz and 155 MSPS

* Low power: 238 mW @ 80 MSPS 1.8 V supply operation