CY7C1021D-10ZSXI High-speed SRAM, 1 Mb (64 K x 16), 5 V, 10ns, TSOP-44

High-Speed CMOS Static RAM 5V 64kx16 10ns TSOP44(II)

Functional Description: The CY7C1021D is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A15). Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 10 for a complete description of read and write modes. The CY7C1021D device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels.

Features: - Temperature Ranges: Industrial: -40 °C to 85 °C - Pin and Function Compatible with CY7C1021B - High Speed: taa = 10 ns - Low Active Power: Icc = 80 mA at 10 ns - Low CMOS Standby Power: Isb2 = 3 mA - 2.0 V Data Retention - Automatic Power Down when Deselected - CMOS for Optimum Speed and Power - Independent Control of Upper and Lower Bits - Available in Pb-free 44-pin 400-Mil Wide Molded SOJ and 44-pin TSOP II Packages