ZL30672

The ZL30672 offers 2 channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board (“pizza box”) applications where a timing device needs to have features of both a timing and a line card PLL.

Log in to your MyMicrochip account (with SDE enabled) and request for data sheet and the following application notes.

AN3467 Crystals and Oscillators for Next Generation Timing Solutions

ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices

ZLAN-656 Redwood PSNR

ZLAN-664 Board Design Recommendations for Redwood

ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood

ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package

ZLAN-724 Phase Measurement Compensation for Redwood

ZLAN-728 Indirect Read and Write Procedure