Band Class 0, 1, and 10 cdma2000 Femtocell Transceiver

The MAX2553 is a complete single-chip RF-to-bits and bits-to-RF radio transceiver. The device is compliant with the 3GPP2 C.S0010-D femtocell standard for Band Class 0, 1, and 10. It is equipped with multiple receive inputs and transmit outputs for low band, high band, and macrocell monitoring (see Table 1 in the full data sheet).

This fully integrated transceiver facilitates compact radio designs for dongle and stand-alone femtocell products by minimizing external component count. Maxim's MAX-PHY serial interface is used to drastically reduce IC pin count, while worldwide field-proven architecture accelerates time to product deployment.

The MAX2553 features unparalleled receive blocker performance and industry's lowest noise figure for higher data rates and range. Low-power operational modes are available to minimize power consumption. The transmitter is designed to deliver EVM far exceeding the standard requirement at 0dBm.

The MAX2550–MAX2553 is a family of pin-compatible transceivers to cover all major WCDMA and cdma2000® bands. All parts are controlled through a 4-wire interface. The MAX2553 is packaged in a compact 7mm x 7mm TQFN and covers the -40°C to +85°C extended temperature range. A complete radio reference design is available to facilitate custom designs.

Applications

* cdma2000/1xEVDO Band Class 0, 1, and 10 Femtocells

* Single-Chip Femtocell Radio Transceiver

* cdma2000/1xEVDO Band Class 0, 1, and 10 Operation

* 3GPP2 C.S0010-D Femtocell Standard Compliant

* Multiple LNA Inputs for PCS and CELL Macrocell Monitoring

* High Level of Integration

* On-Chip Fractional-N Frequency Synthesizers for LO Generation

* No Tx or SAW Filters Required

* Integrated PA Drivers for Lower Cost Power Amplifier Designs

* 12-Bit AFC DAC to Control TCXO

* On-Chip Temperature Sensor

* Three General-Purpose Outputs

* Reference Clock with Selectable CMOS and Low Swing Output

* PLL Lock Detect Output Through GPO3

* Optimized Receiver Performance

* Exceptional Receive Sensitivity

* High Dynamic Range Sigma-Delta ADCs Allow Simple AGC Implementation with Switched Gain States

* Optimized Transmitter Performance

* Factory Calibrated for Gain, Carrier Leakage, and Sideband Suppression

* 10-Bit Gain Control Resolution for Better Power Accuracy

* 60dB Gain Control Range

* ACPR and EVM Compliance at 0dBm Output Power

* Loopback Operating Mode from Tx Baseband Input to Rx Baseband Output

* MAX-PHY Serial Digital Interface with Single-Bit I and Q Streams

* SPI™ Read-Write Functionality

* Operation Controlled by 4-Wire Serial Interface

* Low-Cost, 7mm x 7mm TQFN Package