DG407 16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers

* oData acquisition systems

* oAudio signal routing

* oMedical instrumentation

* oATE systems

* oBattery powered systems

* oHigh-rel systems

* oSingle supply systems

* oSampling speed is limited by two consecutive events: the transition time of the multiplexer, and the settling time of the sampled signal at the output.tTRANS is given on the data sheet. Settling time at the load depends on several parameters: RDS(on) of the multiplexer, source impedance, multiplexer and load capacitances, charge injection of the multiplexer and accuracy desired.The settling time for the multiplexer alone can be derived from the model shown in figure 5. Assuming a low         impedance signal source like that presented by an op amp or a buffer amplifier, the settling time of the RC network for a given accuracy is equal to nτ:

* oThe maximum sampling frequency of the multiplexer is:

* o(1)

* owhere N = number of channels to scan tSETTLING = nτ = n x RDS(on) x CD(on)

* oFor the DG406 then, at room temp and for 12-bit accuracy, using the maximum limits:

* o(2)

* oor

* o(3)

* oFrom the sampling theorem, to properly recover the original signal, the sampling frequency should be more than twice the maximum component frequency of the original signal. This assumes perfect bandlimiting. In a real application  sampling at three to four times the filter cutoff frequency is a good practice.Therefore from equation 2 above:

* o(4)

* oFrom this we can see that the DG406 can be used to sample 16 different signals whose maximum component frequency can be as high as 173 kHz. If for example, two channels are used to double sample the same incoming signal then its cutoff frequency can be doubled.

* oThe block diagram shown in figure 6 illustrates a typical data acquisition front end suitable for low-level analog signals.     Differential multiplexing of small signals is prefe