High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support

The HMC7044B, which is the revised version of the HMC7044, is a high performance, dual loop, integer N jitter attenuator capable of performing reference selection and generation of ultra-low phase noise frequencies for high-speed data converters with either parallel or serial (JESD204B and JESD204C type) interfaces. In the HMC7044B, the phase alignment of the outputs on edge cases such as temperature and supply voltage is improved. The HMC7044B features two integer mode PLLs and overlapping onchip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044B provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).

The DCLK and SYSREF clock outputs of the HMC7044B can be configured to support signaling standards, such as CML, LVDS, LVPECL, and LVCMOS, and different bias settings to offset varying board insertion losses.

APPLICATIONS

* JESD204B and JESD204C clock generation

* Cellular infrastructure (multicarrier GSM, LTE, W-CDMA)

* Data converter clocking

* Microwave baseband cards

* Phase array reference distribution

* Ultra-low rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz

* Noise floor: −156 dBc/Hz at 2457.6 MHz

* Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output

* Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2

* Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz

* JESD204B- and JESD204C-compatible system reference (SYSREF) pulses

* Narrow-band, dual core VCOs

* 25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels

* SPI-programmable phase noise vs. power consumption