3.3V 128K x 36 ZBT Synchronous Pipelined SRAM

The 71V546 3.3V CMOS SRAM, organized as 128K x 36 bits, is designed to eliminate dead bus cycles when turning the bus around between reads and writes or writes and reads. Thus, it has been given the name ZBT™, or Zero Bus Turnaround. The 71V546 contains data I/O, address, and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.