Singled-ended input RF-sampling 12-bit ADC with dual-channel 5.2 GSPS or single-channel 10.4 GSPS

The ADC12DJ5200SE is an RF-sampling, giga-sample, analog-to-digital converter (ADC) with integrated input baluns. The ADC12DJ5200SE can be configured as a dual-channel, 5.2 GSPS ADC or single-channel, 10.4 GSPS ADC. The -3dB input frequency range of 2 to 6.3GHz enables direct RF sampling of S-band and C-band for frequency agile systems.

The ADC12DJ5200SE uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.

Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.