Input Mux - 2:1 Differential, 1.8 V, Clock / Data Fanout Buffer - 1:6 CML, 1.2 V / 1.8 V

The NB7V586M is a differential 1-to-6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INxb inputs incorporate internal 50-ohm termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The INx/INxb inputs and core logic are powered with a 1.8 V supply. The NB7V586M produces six identical differential CML output copies of Clock or Data. The outputs are configured as three banks of two differential pair. Each bank (or all three banks) have the flexibility of being powered by any combination of either a 1.8 V or 1.2 V supply. The 16 mA differential CML output structure provides matching internal 50-ohm source terminations and 400 mV output swings when externally terminated with a 50-ohm resistor to VCCOx. The 1:6 fanout design was optimized for low output skew and minimal jitter and is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications operating up to 6 GHz or 10 Gb/s typical. The VREFAC reference outputs can be used to rebias capacitor-coupled differential or single-ended input signals. The NB7V586M is offered in a low profile 5mm x 5mm 32-pin Pb-Free QFN package.