Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination

NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.25 GHz, respectively. The NB4N527S has a wide input common mode range of GND+50 mV to VCC-50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components. The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.