Dual 4-bit static shift register

The HEF4015B is a dual edge-triggered 4-bit static shift register (serial-to-parallel converter). Each shift register has a serial data input (nD), a clock input (nCP), four fully buffered parallel outputs (Q0 to Q3) and an overriding asynchronous master reset input (nMR). Information present on nD is shifted to the first register position, and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of nCP. A HIGH on nMR clears the register and forces Q0 to Q3 to LOW, independent of nCP and nD. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.