OC-12/STM-4 AND OC-3/STM-1 CLOCK/DATA RECOVERY DEVICE

The 894D115I-04 is a clock and data recovery circuit. The device is designed to extract the clock signal from a NRZ-coded STM-4 (OC-12/STS-12) or STM-1 (OC-3/STS-3) input data signal. The output signals of the device are the recovered clock and retimed data signals. Input and output are differential signals for best signal integrity and to support high clock and data rates. All control inputs and outputs are single-ended signals. An internal PLL is used for clock generation and recovery. An external clock input is provided to establish an initial operating frequency of the clock recovery PLL and to provide a clock reference in the absence of serial input data. The device supports a signal detect input and a lock detect output. A bypass circuit is provided to facilitate factory tests.