Low Phase Noise, Triple Output Clock Distribution Divider/Driver

The LTC6954 is a family of very low phase noise clock distribution parts. Each part has three outputs and each output has an individually programmable frequency divider and delay. There are four members of the family, differing in their output logic signal type:

LTC6954-1: Three LVPECL outputs

LTC6954-2: Two LVPECL and one LVDS/CMOS outputs

LTC6954-3: One LVPECL and two LVDS/CMOS outputs

LTC6954-4: Three LVDS/CMOS outputs

Each output is individually programmable to divide the input frequency by any integer from 1 to 63, and to delay each output by 0 to 63 input clock cycles. The output duty cycle is always 50%, regardless of the divide number. The LVDS/CMOS outputs are jumper selectable via the OUTxSEL pins to provide either an LVDS logic output or a CMOS logic output.

The LTC6954 also features Linear Technology’s EZSync system for perfect clock synchronization and alignment every time.

All device settings are controlled through an SPI-compatible serial port.

Applications

* Clocking High Speed, High Resolution ADCs, DACs and Data Acquisition Systems

* Low Jitter Clock Distribution

* Low Noise Clock Distribution: Suitable for High Speed/High Resolution ADC Clocking

* Additive Jitter < 20fsRMS (12kHz to 20MHz)

* Additive Jitter < 85fsRMS (10Hz to Nyquist)

* 1.8GHz Maximum Input Frequency (LTC6954-1 When DELAY = 0)

* 1.4GHz Maximum Input Frequency (LTC6954-1 When DELAY > 0, LTC6954-2, -3, -4)