DSPIC33FJ12MC202-I/SP dsPIC microcontroller, 16-bit, 3.0-3.6 V, 12 KB, 40 MHz, DIP-28

High-Performance, 16-bit Digital Signal Controllers dsPIC33FJ12MC201/202

High-Performance DSC CPU: - Modified Harvard architecture - C compiler optimized instruction set - 16 bit wide data path - 24 bit wide instructions - Linear program memory addressing up to 4M instruction words - Linear data memory addressing up to 64 Kbytes - 83 base instructions, mostly one word/one cycle - Sixteen 16-bit general purpose registers - Two 40-bit accumulators with rounding and saturation options - Flexible and powerful addressing modes: - Indirect - Modulo - Bit-Reversed - Software stack - 16 x 16 fractional/integer multiply operations - 32/16 and 16/16 divide operations - Single-cycle multiply and accumulate: - Accumulator write back for DSP operations - Dual data fetch - Up to ±16-bit shifts for up to 40-bit data

System Management: - Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low-jitter PLL - Power-up Timer - Oscillator Start-up Timer/Stabilizer - Watchdog Timer with its own RC oscillator - Fail-Safe Clock Monitor - Reset by multiple sources

Interrupt Controller: - 5-cycle latency - Up to 26 available interrupt sources - Up to three external interrupts - Seven programmable priority levels - Four processor exceptions

CMOS Technology: - Low-power, high-speed Flash technology - Fully static design - 3.3V (±10%) operating voltage - Industrial and extended temperature - Low power consumption

Digital I/O: - Peripheral Pin Select Functionality - Up to 21 programmable digital I/O pins - Wake-up/interrupt-on-change for up to 21 pins - Output pins can drive from 3.0V to 3.6V - Up to 5V output with open drain configurations on 5V tolerant pins - 4 mA sink on all I/O pins

Power Management: - On-chip 2.5V voltage regulator - Switch between clock sources in real time - Idle, Sleep and Doze modes with fast wake-up

On-Chip Flash and SRAM: - Flash program memory (12 Kbytes) - Data SRAM (1024 bytes) - Boot and General Security for Program Flash

Timers/Capture/Compare: - Timer/Counters, up to three 16-bit timers: - Can pair up to make one 32-bit timer - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler - Input Capture (up to four channels): - Capture on up, down, or both edges - 16-bit capture input functions - 4-deep FIFO on each capture - Output Compare (up to two channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM Mode

Communication Modules: - 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes - I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking - UART: - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4 character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS

Motor Control Peripherals: - 6-channel 16-bit Motor Control PWM: - Three duty cycle generators - Independent or Complementary mode - Programmable dead time and output polarity - Edge-aligned or center-aligned - Manual output override control - One Fault input - Trigger for ADC conversions - PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode - 2-channel 16-bit Motor Control PWM: - One duty cycle generator - Independent or Complementary mode - Programmable dead time and output polarity - Edge-aligned or center-aligned - Manual output override control - One Fault input - Trigger for ADC conversions - PWM frequency for 16-bit resolution (@ 40 MIPS) = 1220 Hz for Edge-Aligned mode, 610 Hz for Center-Aligned mode - PWM frequency for 11-bit resolution (@ 40 MIPS) = 39.1 kHz for Edge-Aligned mode, 19.55 kHz for Center-Aligned mode - Quadrature Encoder Interface module: - Phase A, Phase B, and index pulse input - 16-bit up/down position counter - Count direction status - Position Measurement (x2 and x4) mode - Programmable digital noise filters on inputs - Alternate 16-bit Timer/Counter mode - Interrupt on position counter rollover/underflow

Analog-to-Digital Converters (ADCs): - 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - Two and four simultaneous samples (10-bit ADC) - Up to six input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity