PIC24HJ12GP201-I/SO PICmicro microcontroller, 16-bit, 3.0-3.6 V, 12 KB, SO-18

PIC24HJ12GP201/202 High-Performance, 16-bit Microcontrollers

High-Performance CPU: - Modified Harvard architecture - C compiler optimized instruction set - 16-bit-wide data path - 24-bit-wide instructions - Linear program memory addressing up to 4M instruction words - Linear data memory addressing up to 64 Kbytes - 71 base instructions, mostly one word/one cycle - Sixteen 16-bit general purpose registers - Flexible and powerful addressing modes - Software stack - 16 x 16 multiply operations - 32/16 and 16/16 divide operations - Up to ±16-bit shifts for up to 40-bit data

Operating Range: - Up to 40 MIPS operation (@ 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C)

Interrupt Controller: - 5-cycle latency - Up to 21 available interrupt sources - Up to three external interrupts - Seven programmable priority levels - Four processor exceptions

System Management: - Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low-jitter PLL - Power-up Timer - Oscillator Start-up Timer/Stabilizer - Watchdog Timer with its own RC oscillator - Fail-Safe Clock Monitor (FSCM) - Reset by multiple sources

Power Management: - On-chip 2.5V voltage regulator - Switch between clock sources in real time - Idle, Sleep, and Doze modes with fast wake-up

Digital I/O: - Peripheral Pin Select Functionality - Up to 21 programmable digital I/O pins - Wake-up/Interrupt-on-Change for up to 21 pins - Output pins can drive from 3.0V to 3.6V - Up to 5V output with open drain configurations on 5V tolerant pins - 4 mA sink on all I/O pins

On-Chip Flash and SRAM: - Flash program memory (12 Kbytes) - Data SRAM (1024 bytes) - Boot and General Security for Program Flash

Communication Modules: - 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes - I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking - UART: - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS

Analog-to-Digital Converters (ADCs): - 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - Two and four simultaneous samples (10-bit ADC) - Up to 10 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity

CMOS Flash Technology: - Low-power, high-speed Flash technology - Fully static design - 3.3V (±10%) operating voltage - Industrial and extended temperature - Low power consumption

Packaging: - 18-pin PDIP/SOIC - 28-pin SPDIP/SOIC/QFN/SSOP