CMOS, 24-Bit Sigma-Delta, Signal Conditioning ADC with 2 Analog Input Channels

The AD7712 is a complete analog front end for low frequency measurement applications. The device has two analog input channels and accepts either low level signals directly from a transducer or high level (±4 × VREF) signals and outputs a serial digital word. It employs a sigma-delta conversion technique to realize up to 24 bits of no missing codes performance. The low level input signal is applied to a proprietary programmable gain front end based around an analog modulator. The high level analog input is attenuated before being applied to the same modulator. The modulator output is processed by an on-chip digital filter. The first notch of this digital filter can be programmed via the on-chip control register allowing adjustment of the filter cutoff and settling time.

Normally, one of the channels will be used as the main channel with the second channel used as an auxiliary input to periodically measure a second voltage. The part can be operated from a single supply (by tying the VSS pin to AGND) provided that the input signals on the low level analog input are more positive than -30 mV. By taking the VSS pin negative, the part can convert signals down to -VREF on this low level input. This low level input, as well as the reference input, features differential input capability.

The AD7712 is ideal for use in smart, microcontroller-based systems. Input channel selection, gain settings and signal polarity can be configured in software using the bidirectional serial port. The AD7712 also contains self-calibration, system calibration and background calibration options and also allows the user to read and to write the on-chip calibration registers.

CMOS construction ensures low power dissipation and a hardware programmable power-down mode reduces the standby power consumption to only 100 µW typical. The part is available in a 24-pin, 0.3 inch wide, plastic and hermetic dual-in-line package (DIP) as well as a 24-lead small outline (SOIC) package.

* Charge Balancing ADC

24 Bits No Missing Codes

±0.0015% Nonlinearity

* High Level and Low Level Analog Input Channels

* Programmable Gain for Both Inputs

Gains from 1 to 128

Differential Input for Low Level Channel