Sample

Dual-Channel, 12-Bit, 105-MSPS Analog-to-Digital Converter (ADC)

... provided on differential LVDS signal pairs. This ...

Sample

Dual-Channel, 14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)

... provided on differential LVDS signal pairs. These ...

Sample

125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface

... serial data to 5 LVDS outputs without the need ...

Sample

125 to 312.5-MHz FPGA-link deserializer with DDR LVDS parallel interface

... serial data to 5 LVDS outputs without the need ...

Sample

5-MHz to 35-MHz DC-balanced 24-bit FPD-Link II deserializer

... the high-speed I/O. LVDS provides a low-power and ...

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5-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer

... I/O. FPD-Link II LVDS provides a low-power and ...

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1843 to 2160-MHz, 800-fs RMS jitter, precision clock conditioner with integrated VCO

... output mux, and an LVDS or LVPECL output buffer ...

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14-Bit, 80Msps Ultra-Low Power 1.8V ADCs

... or double data rate LVDS. A separate output power ...

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14-Bit, 105Msps Ultra-Low Power 1.8V ADCs

... or double data rate LVDS. A separate output power ...

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14-Bit, 125Msps Ultra-Low Power 1.8V ADCs

... or double-data rate LVDS. A separate output power ...

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1.5-Gbps 4x4 LVDS crosspoint switch

... 1.5 Gbps 4x4 LVDS crosspoint switch optimized for ...

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3.125-Gbps 4x4 LVDS crosspoint switch with TX pre-emphasis & RX equalization

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125-MHz quad M-LVDS line driver

... a high-speed quad M-LVDS line driver designed for ...

Sample

12-Bit, 80Msps Ultralow Power 1.8V ADCs

... or double-data rate LVDS. A separate output power ...

Sample

12-Bit, 105Msps Ultralow Power 1.8V ADCs

... or double-data rate LVDS. A separate output power ...