Sample

Dual 4-Bit D-Type Edge-Triggered Flip-Flops

... and SN74AS876 have preset () inputs and ...

Sample

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset

... low level at the preset () or clear () inputs ...

Sample

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

... low level at the preset () or clear () inputs ...

Sample

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

... low level at the preset () or clear () inputs ...

Sample

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset

... A low level at the preset (PRE\) or clear (CLR ...

Sample

Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset

... low level at the preset () or clear () inputs ...

Sample

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset

Sample

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset

... A low level at the preset (PRE) or clear (CLR ...

Sample

Dual J-K Positive-Edge-Triggered Flip-Flops With Clear and Preset

... A low level at the preset or clear inputs sets or ...

Sample

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

... A low level at the preset and clear inputs sets or ...

Sample

Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset

This dual negative-edge-triggered J-K flip-flop ...

Sample

Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset

... A low level at the preset and clear inputs sets or ...

Sample

Test bus controller

... bit counter can be preset to allow a predetermined ...

Sample

Test-Bus Controllers IEEE Std 1149.1 (JTAG) TAP Masters With 16-Bit Generic Host Interfaces

... bit counter can be preset to allow a predetermined ...

Sample

Enhanced Product Single Positive Edge Triggered D-Type Flip-Flop With Clear And Preset

... A low level at the preset (PRE) or clear (CLR ...