MxFE™ Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC

The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.

APPLICATIONS

* Wireless communications infrastructure

* Microwave point-to-point, E-band and 5G mmWave

* Broadband communications systems

* DOCSIS 3.1 and 4.0 CMTS

* Phased array radar and electronic warfare

* Electronic test and measurement systems

* Flexible, reconfigurable common platform design

* 4 DACs and 4 ADCs (4D4A)

* Supports single, dual, and quad band

* Datapaths and DSP blocks are fully bypassable

* DAC to ADC sample rate ratios of 1, 2, 3, and 4

* On-chip PLL with multichip synchronization

* External RFCLK input option for off-chip PLL

* Maximum DAC sample rate up to 12 GSPS

* Maximum data rate up to 12 GSPS using JESD204C

* Useable analog bandwidth to 8 GHz

* Maximum ADC sample rate up to 4 GSPS

* Maximum data rate up to 4 GSPS using JESD204C

* 7.5 GHz analog input full power bandwidth (−3 dB)

* ADC ac performance at 4 GSPS, input at −2.7 GHz, −1 dBFS

* Full-scale input voltage: 1.4 V p-p

* Noise density: −147.5 dBFS/Hz

* Noise figure: 26.8 dB

* HD2: −67 dBFS

* HD3: −73 dBFS

* Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz

* DAC ac performance at 12 GSPS

* Full-scale output current range: 6.43 mA to 37.75 mA

* Two-tone IMD3 (−7 dBFS per tone): −78.9 dBc

* NSD, single-tone at 3.7 GHz: −155.1 dBc/Hz

* SFDR, single-tone at 3.7 GHz: −70 dBc

* SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps

* 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver Rx (JRx)

* JESD204B compliance with the maximum 15.5 Gbps

* JESD204C compliance with the maximum 24.75 Gbps

* Supports real or complex digital data (8-, 12-, 16-, or 24-bit)