Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator

The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL/LVDS/CML input levels and LVTTL/LVCMOS output levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package makes the EPT21 ideal for applications which require the translation of a clock or data signal.

The VBB output allows the EPT21 to be cap coupled in either single-ended or differential input mode. When single-ended cap coupled, VBB output tied to the D0 input for a non-inverting buffer or the D0 input for an inverting buffer. When cap coupled differentially, VBB output is connected through a resistor to each input pin. If used, the VBB pin should be bypassed to VCC via a 0.01 F capacitor. For additional information see AND8020. For a single-ended direct connection use an external voltage reference source such as a resistor divider. Do not use VBB for a single-ended direct connection.