Translator, 2.5 V / 3.3 V, 5 Gb/s Multi Level, Clock/Data Input to CML, Driver / Receiver / Buffer, with Internal Termination

The NB4L16M is a differential driver/receiver/buffer/translator which can accept LVPECL, LVDS, CML, LVCMOS/LVTTL and produce 400 mV CML output. The device is housed in a 3x3 mm 16 pin QFN package. Differential inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), LVTTL/LVCMOS, CML, or LVDS. The differential 16 mA CML output provides matching internal 50 Ω termination, and 400 mV output swing when externally receiver terminated, 50 Ω to VCC. These features provide transmission line termination on chip, at the receiver and driver end, eliminating any use of additional external components. The VBB, an internally generated voltage supply, is available to this device only. For single ended input configuration, the unused complementary differential input is connected to VBB as a switching reference voltage. The VBB reference output can be used also to re-bias capacitor coupled differential or single ended output signals. For the capacitor coupled input signals, VBB should be connected to the VTD pin and bypassed to ground with a 0.01 µF capacitor. When not used VBB should be left open.