8-bit parallel-in/serial out shift register with Schmitt-trigger inputs

The 74HCS166 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). When PE is HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH on CE disables the CP input. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

All inputs are Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.