Low Skew,1-to-4 Differential-to-LVDS Fanout Buffer

The ICS8543-09 is a low-skew, high-performance 1-to-4 differential-to-LVDS clock fanout buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543-09 provides a low power, low noise, solution for distributing clock signals over controlled impedances of 100Ω. The device has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8543-09 ideal for those applications demanding well-defined performance and repeatability.