MIC68220

The MIC68220 is a dual high peak current LDO regulator designed specifically for powering applications such as FPGA core voltages that require high start-up current with lower nominal operating current. Capable of sourcing 2A of current per channel for start-up. The MIC68220 can also implement a variety of power-up and power-down protocols such as sequencing, tracking, and ratiometric tracking.

The MIC68220 operates from a wide input range of 1.65V to 5.5V, which includes all of the main supply voltages commonly available today. It is designed to drive digital circuits requiring low voltage at high currents (i.e. PLDs, DSP, microcontroller, etc.). The MIC68220 incorporates a delay pin (Delay) for control of power on reset output (POR) at turn-on and power-down delay at turn-off. In addition there is a Ramp Control (RC) pin for either tracking applications or output voltage slew rate adjustment at turn-on and turn-off. This is important in applications where the load is highly capacitive and in-rush currents can cause supply voltages to fail and microprocessors or other complex logic chips to hang up.

The MIC68220 can be configured in two modes. In tracking mode, the output voltage of Vout1 drives the RC2 pin so that the Vout2 tracks Vout1 during turn-on and turn-off. In sequencing mode, POR1 of Vout1 drives the enable pin (EN2) of Vout2 so that it turns on after the Vout1 and turns off before (or after) Vout1. This behavior is critical for power-up and power-down control in multi-output power supplies. The MIC68220 is fully protected offering both thermal and current limit protection, and reverse current protection.