CY62148ELL-55SXI SRAM, 4 Mb (512 K x 8), 5 V, 55ns, SOP-32

4-Mbit (512K × 8) Static RAM, LLPow as 5 V 512kx8 55ns SOP32

Description: The CY62148E is a high performance CMOS static RAM organized as 512 K words by 8-bits. This device features advanced circuit design to provide ultra low standby current. This is ideal for providing More Battery Life™ (MoBL?) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (CE HIGH), Outputs are disabled (OE HIGH), or during an active Write operation (CE LOW and WE LOW). To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the I/O pins. The CY62148E device is suitable for interfacing with processors that have TTL I/P levels. It is not suitable for processors that require CMOS I/P levels.

Features: - Very high speed: 45 ns - Voltage range: 4.5 V to 5.5 V - Pin compatible with CY62148B - Ultra low standby power - Typical standby current: 1 µA - Maximum standby current: 7 µA (Industrial) - Ultra low active power - Typical active current: 2.0 mA at f = 1 MHz - Easy memory expansion with CE, and OE features - Automatic power-down when deselected - Complementary metal oxide semiconductor (CMOS) for optimum speed and power - Available in Pb-free 32-pin thin small outline package (TSOP) II and 32-pin small-outline integrated circuit (SOIC)[1] packages